Austin Guerrero — Electrical Engineering Student

Digital hardware, analog circuits, and the odd vintage computer.

Austin Guerrero is an electrical engineering student at Valparaiso University, transferred in from Purdue University, and originally from Crown Point, Indiana. He works mostly in digital hardware — RTL design in SystemVerilog and FPGA verification — and analog circuit design. He is currently seeking a Summer 2027 internship in electrical or hardware engineering.

Currently seeking a Summer 2027 internship in electrical or hardware engineering.

Contact

Email: austin.guerrero@valpo.edu
Phone: 219-689-7468
GitHub: https://github.com/austinguerrero
LinkedIn: https://www.linkedin.com/in/guerrero-austin
Location: Crown Point, IN

Education

Valparaiso University, Christ Honors College — B.S. Electrical Engineering (Expected August 2028). Current coursework: ECE 263 Linear Circuit Theory I, ECE 221 Digital Logic Design, ECE 211 Technical Writing for ECE, DATA 240 Statistical Analysis.
Purdue University — Electrical Engineering (transferred) (August 2024 – June 2026)
Ivy Tech Community College & Porter County Career and Technical Education — A.S. Computer-Aided Design and General Studies, Summa Cum Laude (May 2024)

Experience

Undergraduate Researcher, Robotic Cybersecurity — Valparaiso University

With Dr. Sami Khorbotly · Fall 2026 – Present

Researching how heartbeat theory can detect and prevent cyber attacks on networked robots.
Testing heartbeat-based monitoring on e-puck and Kilobot swarm-robotics platforms.

Undergraduate Researcher, Volumetric Additive Manufacturing — Valparaiso University

In collaboration with UC Berkeley · August 2026 – Present

Working on the implementation of ultrasonic transducers in the VAM system.
Investigating photopolymerization-based volumetric additive manufacturing.
Supporting experimental design and process optimization to improve print quality and efficiency.

Industrial and Materials Engineering Intern — National Material L.P.

East Chicago, Indiana · May 2025 – June 2026

Built a searchable engineering database of hundreds of steel specifications, cutting material search time by roughly 70%.
Automated material traceability workflows in Microsoft Dynamics AX, improving accuracy and reducing manual errors.

Undergraduate Researcher — Systems-on-Chip Enabled Technologies (SoCET), Purdue University

West Lafayette, Indiana · August 2024 – May 2025

Designed RTL modules in SystemVerilog using finite-state machines and synchronous digital logic.
Simulated and verified FPGA designs, building experience in hardware debugging and digital verification.
Worked alongside graduate researchers and industry engineers on semiconductor and FPGA design methodology.

Projects

Heartbeat Theory: Cybersecurity for Swarm Robots

Undergraduate research with Dr. Sami Khorbotly, Fall 2026 – Present

Using heartbeat theory to detect and prevent cyber attacks on robots, tested on e-puck and Kilobot swarm robots.

Technologies: Cybersecurity, Robotics, Swarm Systems, e-puck, Kilobot

Volumetric Additive Manufacturing (VAM)

Undergraduate research with UC Berkeley, August 2026 – Present

Working on the implementation of ultrasonic transducers in the VAM system, plus experimental design and process optimization for photopolymer volumetric printing. Related open-source tools from the UC Berkeley collaborators: OpenCAL / VAMToolbox on GitHub.

Technologies: Ultrasonic Transducers, Photopolymers, Additive Manufacturing, Experimental Design

FPGA Stopwatch System

VIP SoCET Research Project, May 2025 · Purdue SoCET team on GitHub

Designed a stopwatch in SystemVerilog using finite-state machines and synchronous digital logic. Simulated the functionality, deployed it onto FPGA hardware, then debugged timing and logic issues through waveform analysis.

Technologies: SystemVerilog, RTL Design, FPGA, Finite-State Machines, Waveform Debugging

12-Band Audio Equalizer

ECE 20007 Final Project, December 2025

Built a twelve-band analog equalizer from op-amp band-pass filter stages. Simulated the frequency response in LTspice, tuned each band's gain, then assembled and tested the physical circuit on the bench.

Technologies: Op-Amp Circuits, LTspice, Analog Filters, Frequency Response, Bench Testing

Steel Specification Database

National Material L.P., May 2025 – June 2026

Created a searchable engineering database of hundreds of steel specifications, cutting material search time by roughly 70%, and automated material traceability workflows in Microsoft Dynamics AX.

Technologies: Database Design, Microsoft Dynamics AX, Process Automation, Excel, VBA

EEG / Brain-Computer Interface Research

IEEE Systems, Man and Cybernetics Committee, August 2025 – Present

Ongoing research analysing brain-signal data: signal processing and interpretation of EEG recordings for brain-computer interface work.

Technologies: EEG, Signal Processing, MATLAB, Python, Data Analysis

Interactive Macintosh Portfolio Website

Personal project, 2026

A working System 7 desktop built by hand in a single HTML file with no frameworks: draggable windows, a real Finder with a persistent file system, Chess with an alpha-beta engine, MacPaint, Minesweeper and an animated dogcow.

Technologies: JavaScript, HTML5 Canvas, CSS, Web Audio API, Pixel Art

Courses Taken

Valparaiso University (Fall 2026 · current)

ECE 263 — Linear Circuit Theory I
ECE 221 — Digital Logic Design
ECE 211 — Technical Writing for ECE
DATA 240 — Statistical Analysis

Purdue University (2024 – 2026)

ECE 20001 — Electrical Engineering Fundamentals I
ECE 20007 — Electrical Engineering Fundamentals I Lab
ECE 27000 — Introduction to Digital System Design
ECE 26400 — Advanced C Programming
ECE 20875 — Data Science Using Python
CS 15900 — C Programming
MA 16500 — Analytic Geometry & Calculus I
MA 16600 — Analytic Geometry & Calculus II
MA 26100 — Multivariate Calculus
MA 26500 — Linear Algebra
MA 26600 — Differential Equations
PHYS 17200 — Modern Mechanics

Ivy Tech Community College (2021 – 2024)

SDEV 120 — Computing Logic
MATH 137 — Precalculus: Functions and Trigonometry

Porter County Career Center (2023 – 2024)

DESN 101 — Introduction to Design Technology
DESN 104 — Mechanical Graphics
DESN 105 — Architectural Design I

Lab Reports and Design Projects

ECE 221 Design Project 1: Universal Gates & NOR-Only Half Adder (ECE 221, Fall 2026) — Proved NAND and NOR are universal gates by rebuilding NOT, AND and OR from each, then designed a half adder from two-input NOR gates only. Schematics in OrCAD Capture, waveforms in PSpice. NOR-only half adder schematic (OrCAD Capture). NOT, AND and OR rebuilt from NOR gates only. NOT, AND and OR rebuilt from NAND gates only. PSpice timing diagram of the NOR-gate equivalents. PSpice timing diagram of the NAND-gate equivalents.
ECE 221 Lab 2: Half-Adder Implementation (ECE 221, Fall 2026) — Built the NOR-only half adder on a breadboard with two 74LS02 chips, verified all four input cases with switches and LEDs, and measured a 25 ns input-to-SUM delay on the oscilloscope. Total parts cost: under four dollars. Half adder built on a breadboard with two 74LS02 chips. Oscilloscope capture: 25 ns input-to-SUM delay. Wiring schematic with input switches and LED outputs.
ECE 221 Design Project 2: Logic Minimization: Excess-3 to 2-of-5 Converter (ECE 221, Oct 2026) — Minimized five output functions in Minilog (SOP/POS, single- and multiple-output), then built two designs: a 22-gate minimum-gate version and a 19-gate, five-IC minimum-chip version using don't-cares and shared XOR logic. Both verified in PSpice. Minimum-IC design: 19 gates on five ICs. Minimum-gate design: 22 AND/OR/NOT gates. PSpice simulation of the minimum-IC design. PSpice simulation of the minimum-gate design.
ECE 221 Lab 3: Excess-3 to 2-of-5 Converter in Hardware (ECE 221, Oct 2026) — Moved the code converter onto a breadboard as a NAND-NAND, six-IC circuit. Correct output on all ten valid inputs; the longest five-gate path measured 23.2 ns of propagation delay. Six-IC code converter on the breadboard. Oscilloscope capture: 23.2 ns worst-case delay. NAND-NAND wiring schematic.
ECE 221 Design Project 3: 4-Bit Ripple Adder/Subtractor (ECE 221, Oct 2026) — Designed a one-bit 'full adder plus' cell with an XOR controlled inverter, reduced it to six gates with K-maps, then chained four hierarchical copies into a 2's complement adder/subtractor verified in PSpice. 4-bit adder/subtractor built from four hierarchical cells. One-bit full adder plus cell (OrCAD Capture). PSpice simulation of 3 + 4, 7 − 3 and −5 − (−7). PSpice simulation of the cell across all 16 inputs.
ECE 263 Lab 4: Wheatstone Bridge: Measuring Resistance (ECE 263, Sep 2026) — Measured nine resistors across five decades with three bridge ratios and a galvanometer. Every estimate landed within 2.8% of the DMM reading, and five of nine within 1%. Wheatstone bridge with galvanometer. Bridge vs. DMM percent difference for all nine resistors.
ECE 263 Lab 5: MATLAB and Systems of Equations (ECE 263, Oct 2026) — Used MATLAB as a matrix tool, plotter and circuit solver: plotted 60 Hz sinusoids and solved a nodal-analysis circuit with rref (i5 = 1.352 A). 60 Hz sine and cosine plotted in MATLAB. Nodal-analysis matrix equation solved with rref. MATLAB rref output (i5 = 1.352 A).
ECE 263 Lab 6: Mesh and Nodal Analysis (ECE 263, Oct 2026) — Solved a two-source, six-resistor network by hand, in CircuitLab and on the bench. Hand and simulation agreed within 0.05%; after correcting for real source and resistor values, the bench matched within 0.72%. Two-source, six-resistor DC network. CircuitLab simulation with meters on every node and mesh.
ECE 263 Lab 7: Thevenin Equivalents & Maximum Power Transfer (ECE 263, Oct 2026) — Found the Thevenin equivalent of a ten-resistor network three ways (all within 1.1%, and within 1.5% of simulation), then verified maximum power transfer at a matched load: 73.6 mW measured vs. 74.67 mW theoretical. Load power vs. load resistance: peak at R_L = R_TH. R_TH from three measurement methods vs. simulation. Two-source, ten-resistor bridge network. CircuitLab model of the original circuit. Thevenin equivalent with a 100 Ω load. Thevenin equivalent with a matched 338.2 Ω load. Thevenin equivalent with an 820 Ω load.

Technical Skills

Electrical

Circuit Analysis and Design
LTspice Simulation
Oscilloscopes and Lab Bench Instrumentation
Soldering and Breadboarding

Hardware

Digital Logic Design (K-maps, Minilog, 74-series ICs)
OrCAD Capture and PSpice
Ultrasonic Transducers
SystemVerilog / RTL Design
FPGA and Digital Logic
AutoCAD and SolidWorks (CSWA certified)
KiCAD PCB Layout

Software

CircuitLab
Statistical Analysis
Technical Writing (IEEE-style lab reports)
MATLAB
Python
C
Excel, VBA and Pandas

Leadership and Involvement

IEEE — Systems, Man and Cybernetics Committee (August 2025 – Present) — Research analysing brain-signal data (EEG / brain-computer interface).
American Society of Mechanical Engineers (ASME) (August 2025 – Present)
Purdue “All-American” Marching Band (August 2025 – Present) — Nationally recognised ensemble; teamwork and precision under pressure.
Jazz Education Network, Purdue Chapter (August 2024 – Present) — Co-founder.
Student Mentor Ambassador, Porter County Career and Technical Education (August 2023 – May 2024) — Led tours for district leaders, military personnel and industry partners.

Awards and Honors

Purdue Tech Point Foundation for Youth — Full Ride Scholarship — March 2024
SkillsUSA Additive Manufacturing — Indiana State Finalist and National Qualifier — April 2024

About this website

This portfolio is an interactive recreation of a classic Macintosh desktop, designed and built by Austin Guerrero as a single HTML file with no frameworks. It includes draggable windows, a working Finder with a persistent file system, Chess against an alpha-beta engine, MacPaint, Minesweeper, an alarm clock, and Clarus the dogcow.

Plain-text version of this profile